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News
IDT Extends 1.8 V RF Timing Family with Dual-Channel Buffer Devices that Deliver High Performance, Low Power
2016-11-28 | ReturnEach of the devices’ two independent buffer channels offers up to eight low-skew outputs. Effective isolation between channels minimizes noise coupling. AC characteristics such as propagation delay are matched between channels.
Delivering up to 50 percent lower power than comparable competitive devices, IDT’s dual-channel buffers allow board designers to reduce power consumption while maintaining clock performance. The buffers also enable engineers to move to lower supply rails in support of deeper submicron silicon processes.
“Relative to system timing distribution, RF designers no longer have to make power consumption trade-offs at the benefit of optimizing signal to noise ratio,” said Kris Rausch, general manager, timing products, at IDT. “These new devices offer superb AC characteristics at a low 1.8 V power supply; a combination that assists designers in maintaining optimum signal-to-noise performance as well as lower power consumption and less heat dissipation.”
The new devices enable two different signals to be buffered while remaining synchronous with one another; one channel can be used for a clock, the other for a synchronization signal or data, as applicable in device clock and SYSREF signal distribution in JESD204B applications. The power reduction allows higher system packing densities, saves cost in the power supply and cooling, and delivers lower power footprints.
The buffers’ low additive phase jitter, high spurious attenuation and low clock output skew are combined with high clock frequency support. Their compatibility with LVDS devices make them easy to use, and they are compatible in pin and function to equivalent industry standard 2.5 V and 3.3 V parts from IDT.
The latest members of the 8P34S buffer family join five previously introduced single-channel members.
Source:http://www.idt.com/